1. Field of the Invention
This invention relates to divide-by-N counters and more particularly to a divide-by-N circuit using both a synchronous down-counter and a ripple down-counter.
2. Description of the Prior Art
A divide-by-N counter will divide by a specific number of counts. That is, for N clock pulses put into the circuit, only one output pulse is generated. If an M bit binary counter is used in the divide-by-N circuit, N must be less than 2.sup.M.
A synchronous counter is one in which all bits of the counter change state simultaneously in response to a common clock. Since all flip-flops change simultaneously, the output (or count or state) can be decoded quickly because there is no count propagation to wait for. A binary synchronous down-counter is one in which each stage will change if the preceding higher frequency stage is going to make a zero to one transition with the next clock pulse. A synchronous down-counter is designed by using shift register bits with additional logic gating at their input terminals which will cause the above-mentioned output changes to occur.
Ripple counters use the output and its inverse of a counting element, a toggle flip-flop, to drive the two-phase clock input of the following counting element. In ripple counters, the flip-flops operate in a toggle mode (i.e., they change with each clock pulse), with the outputs of each flip-flop driving the clock inputs of the following stage. A limitation of all ripple counters is that some state changes require a transition to ripple through many or all stages of the counter. In a down-counter each toggle flip-flop changes state on each zero to one transition of the previous stage. The counter is implemented by connecting the clock input of each stage to the Q output of the previous stage, and the clock input to the Q output. (This assumes a two-phase toggle flip-flop which changes on the clock falling edge.) The propagation delays through the counting elements are added together. In a long high-speed counter, the transition of the last stage can be considerably delayed from the input pulse that caused it. This fact forbids the use of "look ahead" or state decoding logic.
In comparison with a synchronous counter, a ripple counter requires less gating to count properly. In ripple counters, the outputs of one flip-flop are used as the clocks to another flip-flop, whereas synchronous counters use the same clock input to drive all flip-flops, but require further logic to determine when to make transitions. Furthermore, in CMOS there is a power savings in using a ripple counter because every bit runs at half the frequency of the preceding bit, rather than at the input clock frequency.
A limitation with the synchronous counter is its speed of operation. Each stage has logic to determine whether it should change with the next clock pulse. This logic must do its job in a little less than one clock cycle so that it is set up for the next clock pulse. Thus, the logic is doing a "look ahead" function but has little time to do so. Two techniques are available. One is called "parallel look ahead" and requires that every stage have gating with inputs from every faster stage. This loads the faster stages and creates multi-input gates, both factors which slow down the circuit. The other technique is called "ripple look ahead," where each stage combines its state with a signal generated in all previous stages to create a signal (called the carry in) that goes to the following stage. This logic is slow because it requires one gate per stage, which is nearly as bad as the delay in a ripple counter.
The present invention has combined the speed independence of a long ripple counter and the high speed state decode of a short, fast synchronous counter to produce a high speed divide-by-N circuit. This invention also keeps the gate delays per clock period low, uses look ahead techniques, and gives more time-consuming operations more time to occur. The last is enabled by gating out a clock pulse at a critical point, thus giving some circuitry nearly two clock periods to respond properly.